Flexible allocation of I/O channels of a hardware component
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United States of America Patent
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Nov 7, 2017
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N/A
app pub date -
Oct 16, 2013
filing date -
Apr 29, 2013
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Abstract
A method for generating software for a hardware component of a measuring, control, or regulating system having a processor, an FPGA, and a plurality of I/O channels. The I/O channels are connected to the FPGA and the FPGA is connected to the processor via a communications interface. The method includes the steps of selecting a first subset of the I/O channels for operation by the FPGA, generating a first application for execution in the FPGA, selecting a second subset of the I/O channels for operation by the processor, and generating a second application for execution on the processor. The step of generating a first application comprises generating code for connecting the second subset of I/O channels to the communications interface. The invention relates in addition to a method for operating a hardware component.
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