High frequency delay lock loop systems
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United States of America Patent
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Oct 31, 2017
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N/A
app pub date -
Aug 12, 2016
filing date -
Jul 31, 2015
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Abstract
The present invention is directed to signal processing system and electrical circuits. According to various embodiments, a DLL system includes a delay line provides multiple output signals associated with different clock phases. The delay line may be adjusted using a pair of bias voltages. A phase detector systems generates the bias voltages using the multiple output signals from the delay line. The multiple output signals include signals associated with the first phase, the last phase, and two adjacent phases. There are other embodiments as well.
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