Signal processor suitable for low intermediate frequency (LIF) or zero intermediate frequency (ZIF) operation
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United States of America Patent
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Oct 24, 2017
Grant Date -
Jul 13, 2017
app pub date -
Mar 28, 2017
filing date -
Sep 30, 2009
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Abstract
A signal processor for a radio frequency (RF) receiver includes a signal processing path having first and second programmable gain amplifiers and first and second offset correction circuits. The first offset correction circuit receives a first digital offset correction word and corrects a first offset of the first programmable gain amplifier by adding a first value corresponding to the first digital offset correction word to an input of the first programmable gain amplifier. The second offset correction circuit receives a second digital offset correction word and corrects a second offset of the second programmable gain amplifier by adding a first value corresponding to the second digital offset correction word to an input of the second programmable gain amplifier. A controller measures offsets of the first and second programmable gain amplifiers during a calibration, and provides the first and second offset correction words in response to the offsets.
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