Semiconductor heterostructure with stress management
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United States of America Patent
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Oct 24, 2017
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app pub date -
Dec 28, 2016
filing date -
Apr 15, 2014
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Abstract
A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.
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