Antifuse-type one time programming memory cell and array structure with same
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United States of America Patent
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Oct 24, 2017
Grant Date -
Feb 23, 2017
app pub date -
Jan 13, 2016
filing date -
Aug 18, 2015
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Abstract
An antifuse-type OTP memory cell has following structures. A first doped region, a second doped region, a third doped region and a fourth doped region are formed in a well region. A gate oxide layer covers the surface of the well region. A first gate is formed on the gate oxide layer and spanned over the first doped region and the second doped region. The first gate is connected with a word line. A second gate is formed on the gate oxide layer and spanned over the second doped region and the third doped region. The second gate is connected with an antifuse control line. A third gate is formed on the gate oxide layer and spanned over the third doped region and the fourth doped region. The third gate is connected with an isolation control line.
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