Fan-out wafer level chip package structure and manufacturing method thereof
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United States of America Patent
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Oct 24, 2017
Grant Date -
May 5, 2016
app pub date -
Jul 3, 2015
filing date -
Oct 31, 2014
priority date (Note) -
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Abstract
A fan-out wafer level chip package structure and the manufacturing method thereof are provided. The method includes the steps of providing a supporting plate having a removable tape formed on the supporting plate, placing a plurality of chips on the removable tape, applying an adhesive layer on a back surface of each of the chips, providing a conductive cover for covering all chips and isolating the chips from each other by a plurality of partitions, injecting a molding compound into an inside of the conductive cover and curing the molding compound for forming an encapsulation, separating the encapsulation from the supporting plate, forming a connection layer on an active surface of each of the chips to establish electrical connections, and performing a cutting process to divide the encapsulation into a plurality of the package structures.
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