Non-volatile split gate memory cells with integrated high K metal gate logic device and metal-free erase gate, and method of making same
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United States of America Patent
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Oct 17, 2017
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app pub date -
Jun 13, 2016
filing date -
Jul 21, 2015
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Abstract
A method of forming split gate non-volatile memory cells on the same chip as logic and high voltage devices having HKMG logic gates. The method includes forming the source and drain regions, floating gates, control gates, and the poly layer for the erase gates and word line gates in the memory area of the chip. A protective insulation layer is formed over the memory area, and an HKMG layer and poly layer are formed on the chip, removed from the memory area, and patterned in the logic areas of the chip to form the logic gates having varying amounts of underlying insulation.
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