Power supply transient performance (power integrity) for a probe card assembly in an integrated circuit test environment
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United States of America Patent
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Oct 17, 2017
Grant Date -
Aug 31, 2017
app pub date -
Feb 26, 2016
filing date -
Feb 26, 2016
priority date (Note) -
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Abstract
The present invention describes essentially three different embodiments for the implementation of low impedance (over frequency) power delivery to a die. Such low impedance to a high frequency allows the die to operate at package-level speed, thus reducing yield loss at the packaging level. Each embodiment addresses a slightly different aspect of the overall wafer probe application. In each embodiment, however, the critical improvement of this disclosure is the location of the passive components used for supply filtering/decoupling relative to prior art. All three embodiments require a method to embed the passive components in close proximity to the pitch translation substrate or physically in the pitch translation substrate.
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