High order hybrid phase locked loop with digital scheme for jitter suppression
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United States of America Patent
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Oct 10, 2017
Grant Date -
Sep 14, 2017
app pub date -
Mar 9, 2016
filing date -
Mar 9, 2016
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Abstract
A method for filtering noise. The method may include obtaining an output signal from a phase locked loop (PLL) device. The method may include determining, using a digital phase detector and the output signal, an amount of PLL error produced by the PLL device. The method may include filtering, using a delay element and a digital filter, a portion of the amount of PLL error from the output signal to produce a filtered signal in response to determining the amount of PLL error produced by the PLL device.
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