Simultaneous and selective wide gap partitioning of via structures using plating resist
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Oct 3, 2017
Issued Date -
N/A
app pub date -
Mar 11, 2014
filing date -
Mar 4, 2005
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.
First Claim
Other Claims data not available
Family
International Classification(s)
- 2014 Application Filing Year
- H05K Class
- 5122 Applications Filed
- 4182 Patents Issued To-Date
- 81.65 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 9 Citation Count
- H05K Class
- 18.22 % this patent is cited more than
- 8 Age
Maintenance Fees
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|---|---|---|---|---|
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Apr 3, 2025 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Apr 3, 2029 |
