Non-volatile memory and fabricating method thereof
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United States of America Patent
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Oct 3, 2017
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N/A
app pub date -
Mar 4, 2015
filing date -
Dec 25, 2014
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Abstract
A non-volatile memory includes a substrate, a stacked structure, a channel layer, and a second dielectric layer. The stacked structure includes a first dielectric layer and a plurality of memory cells. The first dielectric layer is disposed on the substrate. The memory cells are stacked on the first dielectric layer. Each of the memory cells includes two first conductive layers and a charge storage structure. The charge storage structure is disposed between the two first conductive layers. The charge storage structures in the vertically adjacent memory cells are separated from each other. The channel layer is disposed on a sidewall of the stacked structure and connected to the substrate. The second dielectric layer is disposed between the channel layer and the first conductive layers.

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Patent Owner(s)
Patent Owner | Address | |
---|---|---|
POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION | HSINCHU |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Chen, Chun-Hung | Hsinchu County, TW | 246 | 1469 |
Chiu, Ta-Chien | Miaoli County, TW | 5 | 16 |
Chu, Chien-Lung | Hsinchu, TW | 13 | 75 |
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