Semiconductor device and electronic device
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United States of America Patent
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Oct 3, 2017
Grant Date -
Jun 9, 2016
app pub date -
Dec 1, 2015
filing date -
Dec 8, 2014
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Abstract
In a configuration including a memory cell that retains multilevel data by controlling the on/off state of a transistor, correct data can be read out even if a potential of data retained by turning off the transistor is changed. The memory cell controls writing or retention of data corresponding to one of a plurality of potentials by controlling an on/off state of the transistor. The write voltage generator circuit outputs a first write voltage of data to be written to the memory cell. The write voltage generator circuit obtains a read voltage of the data by reading the first write voltage written to the memory cell. The write voltage generator circuit generates a second write voltage by correcting a change of the first write voltage caused by turning off the transistor, and outputs the second write voltage to the memory cell.
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