All-digital-phase-locked-loop having a time-to-digital converter circuit with a dynamically adjustable offset delay
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United States of America Patent
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Sep 26, 2017
Grant Date -
Jun 23, 2016
app pub date -
Dec 20, 2015
filing date -
Dec 19, 2014
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Abstract
An all-digital-phase-locked-loop (ADPLL) includes a digitally controlled oscillator (DCO) arranged to generate a DCO output signal, and a feedback loop comprising a set of components for controlling the DCO. The set of components comprise: a time-to-digital converter (TDC) arranged to generate a TDC output code indicative of the phase difference between the reference signal and the enable signal measured within the predetermined observation window; a subset of components arranged to generate the enable signal from the DCO output signal; and an offset calibration system connected to the TDC output, which when activated is arranged to evaluate the difference between the first and second offset delay values by monitoring the TDC output code generated over a predetermined period of time, and to adjust the difference to position the predetermined observation window with respect to the reference signal.
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