Resistive memory architecture and devices
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United States of America Patent
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Sep 19, 2017
Issued Date -
Nov 26, 2015
app pub date -
Mar 9, 2015
filing date -
May 20, 2014
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Abstract
Providing a high-density two-terminal memory architecture(s) having performance benefits of two-terminal memory and relatively low fabrication cost, is described herein. By way of example, the two-terminal memory architecture(s) can be constructed on a substrate, in various embodiments, and comprise two-terminal memory cells formed within conductive layer recess structures of the memory architecture. In one embodiment, a conductive layer recess can be created as a horizontal etch in conjunction with a vertical via etch. In another embodiment, the conductive layer recess can be patterned for respective conductive layers of the two-terminal memory architecture.
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