Circuit and method for generation of a clock signal with duty-cycle adjustment
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United States of America Patent
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Sep 12, 2017
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app pub date -
May 16, 2016
filing date -
Dec 23, 2015
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Abstract
A clock-signal generator circuit, for generating an output clock signal starting from an input clock signal, includes: a monostable stage having a clock input configured to receive the input clock signal, a control input configured to receive a control signal, and an output configured to supply the output clock signal having a duty cycle variable as a function of the control signal; and a feedback loop, operatively coupled to the monostable stage for generating the control signal as a function of a detected value, and of a desired value, of the duty cycle of the output clock signal.
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