Floating-gate transistor array for performing weighted sum computation
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United States of America Patent
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Sep 12, 2017
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Aug 14, 2014
filing date -
Aug 14, 2014
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Abstract
A weighted sum is a key computation for many neural networks and other machine learning algorithms. Integrated circuit designs that perform a weighted sum are presented. Weights are stored as threshold voltages in an array of flash transistors. By putting the circuits into a well-defined voltage state, the transistors that hold one set of weights will pass current equal to the desired sum. The current flowing through a given transistor is unaffected by operation of remaining transistors in the circuit.
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