Damage reduction method and apparatus for destructive testing of power semiconductors

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United States of America Patent

PATENT NO 9759763
APP PUB NO 20130027067A1
SERIAL NO

13560233

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Abstract

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A device and method for limiting damage to a semiconductor device under test when the semiconductor device fails during a high current, or high power test is provided. The occurrence of a failure of the device under test is detected, and power applied to the semiconductor device is diverted through a parallel path element upon detection of failure of the semiconductor device.

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Patent Owner(s)

Patent OwnerAddress
INTEGRATED TECHNOLOGY CORPORATION1228 NORTH STADEM DRIVE TEMPE AS 85281

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Baggiore, James Avondale, US 1 14
Clauter, Steve Tempe, US 3 35
Lohr, David Chandler, US 4 125
Rogers, Gary Mesa, US 37 12049
Schwartz, Rodney E Tiki Island, US 8 470

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