LED die with barrier layer
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Sep 5, 2017
Issued Date -
N/A
app pub date -
Oct 9, 2015
filing date -
Jan 21, 2015
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An LED die includes a base, and an N-typed semiconductor layer, an active layer and a P-typed semiconductor layer formed on the base that order. The LED die also includes an N-electrode and a P-electrode. The N-electrode is arranged on the N-typed semiconductor layer and electrically connected therewith. The P-electrode is arranged on the P-typed semiconductor layer and electrically connected therewith. The LED die further includes a barrier layer arranged between the P-typed semiconductor layer and the P-electrode. The barrier layer includes at least two materials of Cr, Ni and Ti. The at least two materials of Cr, Ni and Ti are stacked together to form the barrier layer.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully