Reducing dynamic clock skew and/or slew in an electronic circuit
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United States of America Patent
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Sep 5, 2017
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N/A
app pub date -
Nov 16, 2015
filing date -
Nov 17, 2014
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Abstract
Reducing dynamic clock skew and/or slew in an electronic circuit is provided by: referencing a layout database and/or netlist of a design for the electronic circuit; identifying a set of neighboring buffer pairs with active buffers and adjacent sub-meshes, which are connected by a shorting bar; for each neighboring buffer pair of the set: placing a dummy buffer for each of their active buffers in the adjacent sub-meshes close to the active buffers; routing an input of a first dummy buffer located in a first sub-mesh to an output of an active buffer in a second sub-mesh; routing an input of a second dummy buffer located in the second sub-mesh to an output of an active buffer in the first sub-mesh; and connecting inputs of the first and second dummy buffers to the shorting bar.
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