Dynamic clock rate control for power reduction
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United States of America Patent
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Sep 5, 2017
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N/A
app pub date -
Mar 2, 2015
filing date -
Mar 2, 2015
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Abstract
A pipeline system may adjust clock rates of variable-rate clock signals sent to different processing circuit blocks in a pipeline based on their respective, individual input and output buffer fill levels and processor busy statuses. Variable-rate clock generation circuitry may generate the variable-rate clock signals based on a common clock signal. Additionally, the variable-rate clock generation circuitry may set or adjust the rates of variable-rate clock signals linearly in evenly-spaced increments and decrements.
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