Anti-deadlock circuit for voltage regulator and associated power system
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United States of America Patent
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Sep 5, 2017
Grant Date -
May 11, 2017
app pub date -
Mar 25, 2016
filing date -
Nov 9, 2015
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Abstract
A power system includes a voltage regulating system and a digital circuit. The voltage regulating system receives a power down signal. The voltage regulating system selectively generates an output voltage according to the power down signal. When the digital circuit receives the output voltage, the digital circuit is operated. When the digital circuit is not operated, the power down signal is activated. After the external voltage source is switched on and before a voltage of the external voltage source reaches a fixed voltage, the voltage regulating system ignores the power down signal and generates the output voltage. After the voltage of the external voltage source reaches the fixed voltage, the voltage regulating system generates the output voltage if the power down signal is inactivated; the voltage regulating system stops generating the output voltage if the power down signal is activated.
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