Field programmable gate array based brushless DC motor speed detector
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United States of America Patent
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Aug 22, 2017
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N/A
app pub date -
Jul 22, 2014
filing date -
Jul 22, 2014
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Abstract
A counter is started on the falling edge of a tach pulse. This counter counts to the rising edge of a second tach pulse, such as the next tach pulse. During the duration of the tach pulse the FPGA calculates the RPM of a motor. In this way, during each commutation period, a RPM is calculated. The present system performs a RPM calculation during each commutation period and/or tach pulse duration.
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