Wire bond through-via structure and method
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United States of America Patent
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-
Aug 22, 2017
Issued Date -
N/A
app pub date -
Aug 29, 2016
filing date -
Sep 17, 2010
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer containing an integrated circuit die by taking advantage of conventional wire bonding equipment to provide an electrically conductive path defined by a wire bond segment that is encapsulated in a potting material so as to define an electrically conductive wire bond “through-via” accessible from at least the lower or second surface of the layer.
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International Classification(s)
- 2016 Application Filing Year
- H01L Class
- 27971 Applications Filed
- 23507 Patents Issued To-Date
- 84.05 % Issued To-Date
Cited Art Landscape
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- 0 Citation Count
- H01L Class
- 0 % this patent is cited more than
- 8 Age
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