Stacking arrangement for integration of multiple integrated circuits
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United States of America Patent
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Aug 22, 2017
Grant Date -
Nov 10, 2016
app pub date -
May 4, 2015
filing date -
May 4, 2015
priority date (Note) -
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Abstract
A stacked integrated circuit (IC) system including a substrate, a contour support, and a first and second IC dies. The contour support including a first support frame attached to the substrate defining a first lateral contact surface substantially orthogonal to the substrate, a support plate on the first support frame substantially parallel to the substrate, and a second support frame on the support plate defining a second lateral contact surface substantially orthogonal to the substrate, with the first and second lateral contact surfaces laterally offset from each other. The first integrated circuit die with a side abutting the first lateral contact surface, the second integrated circuit die with a side abutting the second lateral contact surface such that at least a portion of the support plate is between the first and second integrated circuit dies.
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