Apparatuses and methods to perform post package trim
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Aug 22, 2017
Issued Date -
N/A
app pub date -
Nov 12, 2014
filing date -
Nov 12, 2014
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Memory die can be stacked to form a three-dimensional integrated circuit. For example, through-silicon vias (TSVs) can permit signals to pass vertically through the three-dimensional integrated circuit. Disclosed herein are apparatuses and methods to perform post package trimming of memory die, which advantageously permits the memory die to be trimmed after the memory die is stacked, such that test and trimming characteristics are relatively close to that which will be actually be encountered.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully