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Abstract

An interface adapter for facilitating the data communication among computation modules in a Network-on-Chip SoC comprises 1) a FIFO block having certain number of storage cells for temporarily storing the data to be transported between two communicating modules; 2) a TAF-DPS clock generator and a multi-phase generator attached at the FIFO write side for generating the write clock for FIFO and the driving clock for the transmitter, a TAF-DPS clock generator and a multi-phase generator attached at the FIFO read side for generating the read clock for FIFO and the driving clock for the receiver; 3) a write pointer controller and a read pointer controller for reading the FIFO status and controlling the TAF-DPS clock generators at the write side and at the read side, respectively. A design scheme of using said interface adapters in Network-on-Chip SoC design includes a plurality of computation modules, routing modules, said interface adapters, a network of communication link, a network of global clock distribution. Methods of creating the interface adapter and using it in the Network-on-Chip SoC design are also disclosed.

First Claim