QSPI based methods of simultaneously controlling multiple SPI peripherals
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United States of America Patent
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Aug 15, 2017
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app pub date -
Apr 27, 2017
filing date -
Apr 27, 2017
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Abstract
System and method of using a processor driven master Quad-SPI (QSPI) bus or interface to simultaneously and time-synchronously transmit different streams of data from a FIFO buffer to a plurality of different slave SPI interface peripherals. Here the QSPI interface data ports are configured to simultaneously transmit multiple 1 bit wide streams of different binary data and different chip select commands on an SPI clock cycle synchronized basis. Additional SPI slave peripherals may be controlled by use of additional non-SPI clock synchronized GPIO chip select commands and suitable logic gates. These methods are useful for creating a variety of embedded systems with faster response speeds, such as improved microwave frequency synthesizers with faster frequency changing times.
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