Semiconductor device including embedded crystalline back-gate bias planes, related design structure and method of fabrication
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United States of America Patent
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Aug 8, 2017
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app pub date -
Jan 29, 2016
filing date -
May 23, 2013
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Abstract
A semiconductor device is disclosed. The semiconductor device can include a first dielectric layer disposed on a substrate; a set of bias lines disposed on the first dielectric layer; a second dielectric layer disposed on the first dielectric layer and between the set of bias lines, wherein a thickness of the second dielectric layer is less than a thickness of the first dielectric layer; a patterned semiconductor layer disposed on portions of the second dielectric layer; and a set of devices disposed on the patterned semiconductor layer above the set of bias lines.
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