Method and circuit of pulse-vanishing test
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United States of America Patent
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Aug 1, 2017
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app pub date -
May 19, 2014
filing date -
May 24, 2013
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Abstract
Various aspects of the disclose techniques relate to techniques of testing interconnects in stacked designs. A single-pulse signal, generated by a first circuit state element on a first die, is applied to a first end of an interconnect and captured at a second end of the interconnect using a clock port of a second circuit state element on a second die. A faulty interconnect may cause the single-pulse signal too distorted to reach the threshold voltage of the second circuit element.
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