Trench DMOS transistor with reduced gate-to-drain capacitance

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United States of America Patent

PATENT NO 9716167
SERIAL NO

13032405

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Abstract

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A trench DMOS transistor with a very low on-state drain-to-source resistance and a high gate-to-drain charge includes one or more floating islands that lie between the gate and drain to reduce the charge coupling between the gate and drain, and effectively lower the gate-to-drain capacitance.

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Patent Owner(s)

Patent OwnerAddress
NATIONAL SEMICONDUCTOR CORPORATION2900 SEMICONDUCTOR DRIVE M/S D3-579 SANTA CLARA CA 95051

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Adler, Steven J Saratoga, US 17 332
Foote,, Jr Richard Wendell Burleson, US 4 20
Leng, Yaojian Scarborough, US 74 158

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