3D IC method and device
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United States of America Patent
Stats
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Jul 25, 2017
Grant Date -
Nov 26, 2015
app pub date -
Jul 30, 2015
filing date -
Aug 11, 2005
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose the via, or filled via after bonding.

First Claim
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- 15 United States
- 10 France
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Patent Owner(s)
Patent Owner | Address | |
---|---|---|
INVENSAS BONDING TECHNOLOGIES INC | 3025 ORCHARD PARKWAY SAN JOSE CA 95134 |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Enquist, Paul M | Cary, US | 82 | 5302 |
Fountain,, Jr Gaius Gillman | Youngsville, US | 111 | 4786 |
Tong, Qin-Yi | Durham, US | 47 | 3221 |
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