Timing analysis method for digital circuit design and system thereof
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United States of America Patent
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Jul 18, 2017
Grant Date -
Jan 12, 2017
app pub date -
Jul 6, 2015
filing date -
Jul 6, 2015
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Abstract
A timing analysis method for a digital circuit design, a system and a computer readable storage media thereof are provided. The timing analysis method includes following steps. An integrated circuit (IC) design is obtained, wherein the IC is operated in a plurality of operating modes. A plurality of extracted timing models (ETMs) are respectively generated according to the operating modes of the IC design, wherein each of the ETMs includes a none on-chip variation (NOCV) part and an on-chip variation (OCV) part. The ETMs corresponding to the operating modes are integrated into a NOCV ETM and an OCV ETM, wherein the OCV part of the operating modes is not considered when the NOCV ETM is generated. And, a timing checking of the IC design is analyzed according to the NOCV ETM and the OCV ETM.
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