Stacked structure of semiconductor chips having via holes and metal bumps
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United States of America Patent
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Jul 11, 2017
Issued Date -
N/A
app pub date -
Oct 14, 2015
filing date -
Mar 6, 2013
priority date (Note) -
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Abstract
A stacked structure comprises a semiconductor chip which includes a substrate having at least one substrate via hole penetrating through the substrate; at least one backside metal layer formed on a backside of the substrate covering an inner surface of the substrate via hole and at least part of the backside of the substrate; at least one front-side metal layer formed on the front-side of the substrate and electrically connected to the at least one backside metal layer on a top of at least one of the at least one substrate via hole; at least one electronic device formed on the front-side of the substrate and electrically connected to the at least one front-side metal layer; and at least one metal bump formed on at least one of the backside metal layer and the front-side metal layer.
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