Non-valatile semiconductor memory device and location based erasure methods
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United States of America Patent
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Jul 11, 2017
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N/A
app pub date -
Jul 26, 2016
filing date -
Mar 24, 2016
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Abstract
A non-volatile semiconductor memory device comprising a control circuit is provided, the control circuit performing a data erasure by applying predetermined erase voltages to predetermined blocks of a memory cell array including memory cells disposed on each intersection of a plurality of word lines and a plurality of bit lines, and the control circuit applying the erase voltages to the memory cells to erase data by applying word line voltages different to each other to even-numbered word lines and odd-numbered word lines of the memory cell array except to an edge part thereof, and by applying a voltage different to the word line voltages to the word line in the edge part of the memory cell array.
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