Three-transistor resistive random access memory cells
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United States of America Patent
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Jul 11, 2017
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app pub date -
Dec 9, 2016
filing date -
Sep 30, 2016
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Abstract
A pair of adjacent ReRAM cells in an array includes a first bit line for a row of the array, a second bit line for the row of the array, a p-channel word line associated with two adjacent columns in the array, and an n-channel word line associated with the two adjacent columns. A pair of ReRAM cells in the adjacent columns in the row each includes a switch node, a first ReRAM device connected between the first bit line and the source of a p-channel transistor. The drain of the p-channel transistor is connected to the switch node, and its gate is connected to the p-channel word line. A second ReRAM device is connected between the second bit line and the source of an n-channel transistor. The drain of the n-channel transistor is connected to the switch node, and its gate is connected to the n-channel word line.
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