Network-on-chip using request and reply trees for low-latency processor-memory communication
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United States of America Patent
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Jul 11, 2017
Grant Date -
Jun 5, 2014
app pub date -
Dec 4, 2012
filing date -
Dec 4, 2012
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Abstract
A NOC comprises a die having a cache and a core area, a plurality of core tiles arranged in the core area in a plurality of subsets, at least one cache memory bank arranged in the cache area, whereby the at least one cache memory bank is distinct from each of the plurality of core files. The NOC further comprises an interconnect fabric comprising a request tree to connect to a first cache memory bank of the at least one cache memory bank, each core tile of a first one of the subsets, the first subset corresponding to the first cache memory bank, such that each core tile is connected to the first cache memory bank only, and a reply tree to connect the first cache memory bank to each core tile of the first subset.
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