Phase locked loop frequency calibration circuit and method
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United States of America Patent
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Jul 4, 2017
Grant Date -
Oct 20, 2016
app pub date -
Jun 23, 2016
filing date -
Dec 24, 2013
priority date (Note) -
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Abstract
A phase locked loop frequency calibration circuit and a method are provided. The circuit includes a timer, a counter, a control module, a frequency divider and a voltage controlled oscillator; output of voltage controlled oscillator is connected with first input of frequency divider, output of frequency divider is connected with first input of counter, second input of frequency divider, first input of timer and second input of counter are respectively connected with first output of control module, third input of counter is connected with output of timer, output of counter is connected with first input of control module, a reference clock signal is respectively sent to second input of timer and second input of control module, the number of clocks used by frequency divider to perform frequency division on output clock signal of voltage controlled oscillator is sent to third input of control module.
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