Level-sensitive two-phase single-wire latch controllers without contention
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United States of America Patent
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Jul 4, 2017
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N/A
app pub date -
Jul 1, 2016
filing date -
May 30, 2014
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Abstract
Systems and methods are described for a contention-free single-wire latch controller that includes first and second bidirectional signal pins (e.g., the L and R pins in the FIGS), a latch enable output pin (or signal), E, and a decision element (such as a NAND or a NOR gate). A first driving transistor may be coupled between the first bidirectional signal pin and a power rail. A second driving transistor may be coupled between the second bidirectional signal pin and the power rail. A first half-latch may be coupled to the first bidirectional signal pin. A second half-latch may be coupled to the second bidirectional signal pin.
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