Circuit arrangement and method for coding and/or decoding
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United States of America Patent
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Jun 27, 2017
Grant Date -
Feb 19, 2015
app pub date -
Feb 14, 2014
filing date -
Aug 16, 2011
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Abstract
In order to further develop a circuit arrangement provided for coding and/or decoding a data stream, in particular of up to 24-bit-wide R[ed]G[reen]B[lue] video signals, and a corresponding method in such way that an efficient DC-balanced coding and/or decoding is possible, in particular with the lowest possible overheads,
- at least one coderwith five 5b/6b coder blocks arranged in parallel to each other andwith a 2b/2b coder block arranged in parallel to the 5b/6b coder blocks, and/orat least one decoderwith five 6b/5b decoder blocks arranged in parallel to each other andwith a 2b/2b decoder block arranged in parallel to the 6b/5b decoder blocks are proposed.
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