Merged floating point operation using a modebit
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United States of America Patent
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Jun 27, 2017
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N/A
app pub date -
Dec 29, 2014
filing date -
Jan 25, 2012
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Abstract
A first floating-point operation unit receives first and second variables and performs a first operation generating a first output. A first rounding unit receives and rounds the first output to generate a second output if a control bit is in a first state. A second floating-point operation unit receives a third variable and either the first output or the second output and performs a second operation on the third variable and either the first output or the second output, to generate a third output. The second floating-point operation unit receives and operates on the first output if the control bit is in the first state, or the second output if the control bit is in the second state. A second rounding unit receives and rounds the third output.
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