Managing integrity of framed payloads using redundant signals

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United States of America Patent

PATENT NO 9680606
SERIAL NO

14948203

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Abstract

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A frame error correction circuit may identify and correct errors in data frames provided to a receiver as part of a diversity communications scheme. The frame error correction circuit may further align the data frames so that the data frames can be compared. The frame error correction circuit may perform a bit-wise comparison of the data frames and identify inconsistent bit positions where bits in the data frames differ from one another. Once inconsistent bit positions have been identified, the frame error correction circuit may access a permutation table of permutations of bits at the inconsistent bit positions. In some implementations, the frame error correction circuit uses the permutation table to reassemble permutations of the data frames. In various implementations, the frame error correction circuit performs a CRC of each permutation of the data frames, and provides a valid permutation to a network.

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Patent Owner(s)

Patent OwnerAddress
AVIAT U S INC200 PARKER DRIVE SUITE C100A AUSTIN TX 78728

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Arya, Rishipal San Jose, US 8 18
Brown, Robert Boulder Creek, US 178 2878
Licardie, Sergio Cupertino, US 45 438

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