Volatile memory erasure by the randomization of data stored in memory cells
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United States of America Patent
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Jun 13, 2017
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Apr 8, 2015
filing date -
Apr 8, 2015
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Abstract
The present invention discloses an erasure circuitry, a method for erasing a volatile memory, a volatile memory and a processing unit coupled with an operating system, where the erasure circuitry is adapted to erase the volatile memory at occurrence of a predefined event. The erasure circuitry includes a control unit for initiating a dummy operation to randomize data of one or more memory cells at the occurrence of a predefined event. The control unit is adapted to receive the addresses of the memory blocks from a processing unit via an operating system.
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