Stacked clock-generation circuit
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United States of America Patent
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Jun 13, 2017
Grant Date -
Mar 2, 2017
app pub date -
Aug 24, 2016
filing date -
Aug 31, 2015
priority date (Note) -
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Abstract
An electronic circuit is disclosed for dividing the frequency of a periodic signal, wherein at least one of the memory elements is arranged with its output terminal connected to the input terminal of another memory element wherein the electronic circuit is configured to generate an output signal having a smaller fundamental frequency than the clock signal at at least one of the output terminals. Each memory element is configured to change and hold a voltage at the output terminal based on a voltage at the input terminal at times controlled by a clock signal received at the clock terminal. At least two of the memory elements are stacked in the sense that the bottom terminal of a first memory element is connected to the top terminal of a second memory element to enable the charge to flow from the first memory element to the second memory element.
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