Method of securely erasing a non-volatile semiconductor mass memory, computer system, and computer program product
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United States of America Patent
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Jun 6, 2017
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app pub date -
Nov 26, 2013
filing date -
Jan 28, 2013
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Abstract
A method of securely erasing a non-volatile semiconductor mass memory has a plurality of physical memory units assigned either to a first memory area which can be addressed via an interface of the semiconductor mass memory or to a second memory area which cannot be addressed via the interface, and a controller that changes assignment of the memory units to the first memory area and to the second memory area according to an algorithm that produces wear leveling upon receiving a command to overwrite memory units assigned to the first memory area via the interface.
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