Method of analyzing error rate in system-on-chip
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United States of America Patent
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Jun 6, 2017
Grant Date -
Jul 2, 2015
app pub date -
Dec 30, 2014
filing date -
Dec 30, 2013
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Abstract
In order to improve reliability of a system-on-chip (SoC) through fault tolerance verification, there is provided a method of analyzing an error rate in a system-on-chip (SoC) having at least one internal block obtained by interconnecting two or more gates, comprising: applying an input signal to an input terminal of a certain internal block; defining an input error rate of each gate of the internal block; and defining an output error rate of the internal block based on the input error rate of each gate and an error rate propagating to an output terminal. As a result, there is proposed a method of analyzing a change of the output error rate depending on the input error rate in a gate level in error model development necessary to design and verify a fault-tolerant SoC. Therefore, it is possible to analyze errors in each gate and formularize error rate information modeling including an input/output relationship between each gate of a digital circuit in a library form.
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