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• 15 United States
• 10 France
• 8 Japan
• 7 China
• 5 Korea
• 2 Other

Patent Owner(s)

Patent Owner	Address
GENOMATICA INC	4757 NEXUS CENTER DRIVE SAN DIEGO CA 92121

International Classification(s)

• C12P:FERMENTATION OR ENZYME-USING PROCESSES TO SYNTHESI....
• C12N:MICRO-ORGANISMS OR ENZYMES; COMPOSITIONS THEREOF
• C10L:FUELS NOT OTHERWISE PROVIDED FOR; NATURAL GAS; SYN....

• 2013 Application Filing Year
• C12P Class
• 1593 Applications Filed
• 1388 Patents Issued To-Date
• 87.14 % Issued To-Date

Inventor(s)

Inventor Name	Address	# of filed Patents	Total Citations
Brubaker, Shane	South San Francisco, US	17	450
# of filed Patents : 17 Total Citations : 450
Rude, Mathew A	South San Francisco, US	13	77
# of filed Patents : 13 Total Citations : 77
Schirmer, Andreas W	South San Francisco, US	42	187
# of filed Patents : 42 Total Citations : 187

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Patent Citation Ranking

• 1 Citation Count
• C12P Class

• 51.56 % this patent is cited more than
• 8 Age

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Maintenance Fees

Fee	Large entity fee	small entity fee	micro entity fee	due date
7.5 Year Payment	$3600.00	$1800.00	$900.00	Dec 6, 2024
11.5 Year Payment	$7400.00	$3700.00	$1850.00	Dec 6, 2028

Fee	Large entity fee	small entity fee	micro entity fee
Surcharge - 7.5 year - Late payment within 6 months	$160.00	$80.00	$40.00
Surcharge - 11.5 year - Late payment within 6 months	$160.00	$80.00	$40.00
Surcharge after expiration - Late payment is unavoidable	$700.00	$350.00	$175.00
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DATE PUBLISHED	PUBLICATION/PATENT NO.	PUBLICATION TYPE
June 06, 2017	US,9670512,B2   US9670512B2	GRANTED PATENT AS SECOND PUBLICATION
November 05, 2015	US,20150315617,A1   US20150315617A1	FIRST PUBLISHED PATENT APPLICATION

Full Text

US Patent No: 4892836

Method for manufacturing semiconductor integrated circuits including CMOS and high-voltage electronic devices

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Abstract

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This method, requiring a reduced number of process phases and providing an efficient, high-voltage structure, comprises forming a P-well region of the N-channel transistor of a CMOS device, by means of boron atom implant through a protective mask, forming at least one insulation region surrounding the CMOS device, forming edge regions having the same conductivity type as the insulation region but with a smaller concentration of impurities on at least one part of the insulation region and in the high-voltage electronic devices by means of the same boron atom implant used to form the P-well region.

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Description

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Claims

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Legal Events

 

• FPAY2001
• FPAY1997
• FPAY1993
• I1990
• STCF1989
• F1987
• AS1987
• PD1986

Date	Code	Event	Description
Jun 21, 2001	FPAY	FEE PAYMENT	year of fee payment: 12
Jun 26, 1997	FPAY	FEE PAYMENT	year of fee payment: 8
Jun 24, 1993	FPAY	FEE PAYMENT	year of fee payment: 4
Jan 09, 1990	I	Issuance
Nov 06, 1989	STCF	INFORMATION ON STATUS: PATENT GRANT	free format text: PATENTED CASE
Mar 23, 1987	F	Filing
Mar 10, 1987	AS	ASSIGNMENT	free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:ANDREINI, ANTONIO;CONTIERO, CLAUDIO;GALBIATI, PAOLA;REEL/FRAME:004695/0110 Owner name: SGS MICROELETTRONICA S.P.A., STRADALE PRIMSOLE 50 Effective Date: Mar 10, 1987
Mar 27, 1986	PD	Priority Date