Hierarchical packing of syntax elements
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United States of America Patent
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May 30, 2017
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app pub date -
Oct 13, 2014
filing date -
Oct 6, 2006
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Abstract
A method operates within an integrated circuit device having a plurality of processing lanes. The method determines a first number of packs among one or more first packs associated with a first processing lane of the plurality of processing lanes, associates the first number of packs with a first used field of the first processing lane, determines a second number of packs among one or more second packs associated with a second processing lane of the plurality of processing lanes, and associates the second number of packs with a second used field of the second processing lane.
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