Hierarchical packing of syntax elements

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United States of America Patent

PATENT NO 9667962
SERIAL NO

14513191

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Abstract

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A method operates within an integrated circuit device having a plurality of processing lanes. The method determines a first number of packs among one or more first packs associated with a first processing lane of the plurality of processing lanes, associates the first number of packs with a first used field of the first processing lane, determines a second number of packs among one or more second packs associated with a second processing lane of the plurality of processing lanes, and associates the second number of packs with a second used field of the second processing lane.

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Patent Owner(s)

  • OL SECURITY LIMITED LIABILITY COMPANY

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gulati, Amit Los Altos Hills, US 11 122
Kapasi, Ujval J San Jose, US 16 397
Liu, Yipeng Sunnyvale, US 17 110
Miller, Dan Palo Alto, US 28 306
Seivers, John Lynnfield, US 3 3

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