Programmable partitionable counter
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United States of America Patent
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May 30, 2017
Grant Date -
Dec 12, 2013
app pub date -
Jun 6, 2013
filing date -
Jun 6, 2012
priority date (Note) -
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Abstract
An integrated circuit device for receiving packets. The integrated circuit device includes a programmable partitionable counter that includes a first counter partition for counting a number of the packets, and a second counter partition for counting bytes of the packets. The first counter partition and the second counter partition are configured to be incremented by a single command from the packet processor.
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