Semiconductor device having hierarchically structured bit lines
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United States of America Patent
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May 30, 2017
Grant Date -
May 5, 2016
app pub date -
Jan 11, 2016
filing date -
Aug 14, 2012
priority date (Note) -
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Abstract
Disclosed herein is a device includes first and second memory mats. The first memory mat includes first and defective memory cells and first local bit lines coupled to a first global bit line. Each of the first local bit lines is coupled to associated ones of the first memory cells, one of the first local bit lines is further coupled to the defective memory cell. The second memory mat includes second and redundant memory cells and second local bit lines coupled to a second global bit line. Each of the second local bit lines is coupled to associated ones of the second memory cells, one of the second local bit lines is further coupled to the redundant memory cell. The device further includes a control circuit accessing the redundant memory cell when the access address information coincides with the defective address information that designates the defective memory cell.
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