Techniques for reducing skew between clock signals
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United States of America Patent
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May 23, 2017
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N/A
app pub date -
Jul 28, 2016
filing date -
Nov 28, 2014
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Abstract
A skew reduction circuit includes a first delay circuit that delays a first clock signal to generate a second clock signal and a second delay circuit that delays a third clock signal to generate a fourth clock signal. The skew reduction circuit also includes a time-to-digital converter circuit that measures a skew between the second and fourth clock signals to generate a measurement of the skew between the second and fourth clock signals. The skew reduction circuit adjusts a delay of one of the first or second delay circuits to reduce the skew between the second and fourth clock signals based on the measurement of the skew.
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